1. Field of the Invention
The present invention relates to mixer circuits, and more particularly to a high gain mixer circuit.
2. Description of the Background Art
A conventional Gilbert cell type mixer circuit 1000 will be described with reference to FIG. 12. Mixer circuit 1000 includes a constant current source 1007 which supplies a constant current 2xc3x97IEE, and transistors 1003 to 1006. Here, V1, V2, i1, and i2 denote a first input voltage, a second input voltage, a first output current, and a second output current, respectively.
Transistors 1003,1004 have their emitter terminals connected commonly to each other, and transistors 1005, 1006 also have their emitter terminals connected commonly to each other. Transistors 1003, 1005 have their collector terminals connected commonly to each other, and transistors 1004, 1006 also have their collector terminals connected commonly to each other.
The collector terminal of transistor 1001 is connected to the common emitter terminal of transistors 1003, 1004, and the collector terminal of transistor 1002 is connected to the common emitter terminal of transistors 1005, 1006.
Transistors 1001, 1002 have their emitter terminals connected to constant current source 1007.
Mutually complementary voltages V1+, V1xe2x88x92 are input to the bases of transistors 1001,1002. Voltage V2+ is input to the bases of transistors 1003, 1006, and voltage V2xe2x88x92 is input to the bases of transistors 1004, 1005. Voltages V2+, V2xe2x88x92 are mutually complementary.
First output current il is output from the collector terminals of transistors 1003, 1005, and second output current i2 is output from the collector terminals of transistors 1004, 1006.
The operation will be described in the following. First input voltage V1 and second input voltage V2 are signals having mutually different frequencies f1, f2. The input signals having frequency f1 are converted to the collector currents of transistors 1001, 1002 and amplified by an emitter coupled pair circuit which is formed of transistors 1001, 1002.
The collector currents of transistors 1001, 1002 serve as a tail current for an emitter coupled pair circuit which is formed of transistors 1003, 1004 and for an emitter coupled pair circuit which is formed of transistors 1005, 1006.
The input signals having frequency f2 are amplified respectively by the emitter coupled pair circuit which is formed of transistors 1003, 1004 and by the emitter coupled pair circuit which is formed of transistors 1005, 1006.
This relation is represented by the following equations. Here, VT is a thermal voltage, V1=(V1+)xe2x88x92(V1xe2x88x92), and V2=(V2+)xe2x88x92(V2xe2x88x92). The collector currents of transistors 1001, 1002 are ic1, ic2 which are represented by equations (1), (2).
ic1=2IEE/{1+exp(xe2x88x92V1/VT)}xe2x80x83xe2x80x83(1)
ic2=2IEE/{1+exp(V1/VT)}xe2x80x83xe2x80x83(2)
When the collector currents of transistors 1003, 1004, 1005, and 1006 are ic3, ic4, ic5, and ic6, then ic3 to ic6 are represented by equations (3) to (6).
ic3=ic1/{1+exp(xe2x88x92V2/VT)}xe2x80x83xe2x80x83(3)
ic4=ic1/{1+exp(V2/VT)}xe2x80x83xe2x80x83(4)
ic5=ic2/{1+exp(V2/VT)}xe2x80x83xe2x80x83(5)
ic6=ic2/{1+exp(xe2x88x92V2/VT)}xe2x80x83xe2x80x83(6)
From equations (1) to (6), ic3, ic4, ic5, ic6, V1, and V2 satisfy equations (7) to (10).
ic3=2IEE/[{1+exp(xe2x88x92V1/VT)}xc2x7{1+exp(xe2x88x92V2/VT)}]xe2x80x83xe2x80x83(7)
ic4=2IEE/[{1+exp(xe2x88x92V1/VT)}xc2x7{1+exp(V2/VT)}]xe2x80x83xe2x80x83(8)
ic5=2IEE/[{1+exp(V1/VT)}xc2x7{1+exp(V2/VT)}]xe2x80x83xe2x80x83(9)
ic6=2IEE/[{1+exp(V1/VT)}xc2x7{1+exp(xe2x88x92V2/VT)}]xe2x80x83xe2x80x83(10)
From the forgoing, the differential output current is represented by the following expression.
xe2x80x83i1xe2x88x92i2=ic3+ic5xe2x88x92(ic6+ic4)=2IEExc2x7{tanh(V1/2VT)}xc2x7{tanh(V2/2VT)}xe2x80x83xe2x80x83(11)
Here, tanh can be expanded in series as in equation (12). If x is sufficiently smaller than 1, equation (13) is formed.
tanh(x)=xxe2x88x92xxc2x7xxc2x7x/3xe2x80x83xe2x80x83(12)
tanh(x)≈xxe2x80x83xe2x80x83(13)
The relation between input voltages V1, V2 and differential output currents i1, i2 is represented by equation (14).
i1xe2x88x92i2≈2IEExc2x7(V1/2VT)xc2x7(V2/2VT)xe2x80x83xe2x80x83(14)
In short, mixer circuit 1000 is a circuit for multiplying input voltages V1, V2. That is, input voltages V1, V2 are signals having mutually different frequencies f1, f2. Therefore, by multiplying the two signals, mixer circuit 1000 performs the mixer operation of outputting a signal having a frequency component of the sum (|f1+f2|) or the difference (|f1xe2x88x92f2|) of the frequencies of the two signals.
In the following, each of mixer circuits 1100, 1300 disclosed in Japanese Patent Laying-Open No. 10-322135 will be described.
A low voltage type mixer circuit 1100 will be first described with reference to FIG. 13. Mixer circuit 1100 includes constant current sources 1015, 1016 which supply a constant current IEE, transistors 1011 to 1014, and a 180xc2x0 phase shifter 1017. Here, in1, in2, Out+, and Outxe2x88x92 are a first input signal, a second input signal, a positive output current, and a negative output current, respectively.
Transistors 1011, 1012 have their emitter terminals connected commonly to each other, and transistors 1013, 1014 also have their emitter terminals connected to each other. Transistors 1011, 1013 have their collector terminals connected commonly to each other, and transistors 1012, 1014 also have their collector terminals connected commonly to each other.
The common emitter terminal of transistors 1011, 1012 is connected to constant current source 1015 via a node A. The common emitter terminal of transistors 1013, 1014 is connected to constant current source 1016 via a node B. First input signal in1 is input to node A. Between node A and node B, the 180xc2x0 phase shifter is provided. The common emitter terminal of transistors 1011, 1012 and the common emitter terminal of transistors 1013, 1014 are connected via 180xc2x0 phase shifter 1017.
Signal in2+ is input to the bases of transistors 1011, 1013, and signal in2xe2x88x92 is input to the bases of transistors 1012, 1013. Positive output current Out+ is output from the common collector terminal of transistors 1011, 1013, and negative output current Outxe2x88x92 is output from the common collector terminal of transistors 1012, 1014.
180xc2x0 phase shifter 1017 outputs to node B a signal which has its phase inverted by 180xc2x0 from that of first input signal in1 at node A. If the current component of first input signal in1 is iin1, current iA is iA=IEE+iin1 and current iB B is iB=IEExe2x88x92iin1.
The operation will be described in the following. First input signal in1 and second input signal in2 are signals having mutually different frequencies f1, f2. The common emitter terminal of transistors 1011, 1012 and the common emitter terminal of transistors 1013, 1014 are connected commonly via 180xc2x0 phase shifter 1017. Therefore, differential input currents are obtained at the common emitter terminal of the coupled pair which is formed of transistors 1011, 1012 and at the common emitter terminal of the coupled pair which is formed of transistors 1013, 1014.
Since the complementary input signals are obtained at nodes A, B, the current amplitude is twice as high as the one-side input type described above. Therefore, the mixer operation is performed while suppressing the decrease of conversion gain as much as possible.
Suppose that the collector currents of transistors 1011, 1012, 1013, and 1014 are ic1, ic2, ic3, and ic4, respectively, and vin2=(in2+)xe2x88x92(in2xe2x88x92).
ic1=(IEE+iin1)/{1+exp(xe2x88x92vin2/VT)}xe2x80x83xe2x80x83(15)
ic2=(IEE+iin1)/{1+exp(vin2/VT)}xe2x80x83xe2x80x83(16)
ic3=(IEExe2x88x92iin1)/{1+exp(vin2/VT)}xe2x80x83xe2x80x83(17)
ic4=(IEExe2x88x92iin1)/{1+exp(xe2x88x92vin2/VT)}xe2x80x83xe2x80x83(18)
From the relations of expressions (15) to (18), the output current represented by expression (19) is obtained.                                                                                           (                                      Out                    +                                    )                                -                                  (                                      Out                    -                                    )                                            =                            ⁢                              ic1                +                ic3                -                                  (                                      ic2                    +                    ic4                                    )                                                                                                        =                            ⁢                              2                ⁢                                  iin1                  ·                                      {                                                                  exp                        ⁡                                                  (                                                      vin2                            /                            VT                                                    )                                                                    -                                              exp                        ⁡                                                  (                                                                                    -                              vin2                                                        /                            VT                                                    )                                                                                      }                                                                                                                                        ⁢                              /                                  [                                                            {                                              1                        +                                                  exp                          ⁡                                                      (                                                          vin2                              /                              VT                                                        )                                                                                              }                                        ·                                          {                                              1                        +                                                  exp                          ⁡                                                      (                                                                                          -                                vin2                                                            /                              VT                                                        )                                                                                              }                                                        ]                                                                                                                        =                                ⁢                                  2                  ⁢                                      iin1                    ·                    tan                                    ⁢                                      xe2x80x83                                    ⁢                                      h                    ⁡                                          (                                                                        vin2                          /                          2                                                ⁢                        VT                                            )                                                                                  ⁢                              xe2x80x83                                                                        (        19        )            
Using the relations of expressions (12) and (13), expression (19) is rewritten as in expression (20).
(Out+)xe2x88x92(Outxe2x88x92)≈2iin1xc2x7(vin2/2VT)xe2x80x83xe2x80x83(20)
Therefore, iin1 and vin2 can be multiplied by using mixer circuit 1100. In the case of the one-side input type, the coefficient 2 of iin1 in expression (20) becomes 1.
Since mixer circuit 1100 has one stage of vertically connected transistors other than the constant current source, it operates at a lower power supply voltage as compared with the Gilbert cell type mixer circuit having two stages of vertically connected transistors. It is noted however that 180xc2x0 phase shifter 1017 has to operate at a lower power supply voltage than that of the mixer portion or has to be formed of a passive element.
If 180xc2x0 phase shifter 1017 is formed of a passive element, it has linear properties as compared with the lower stage coupled pair of the Gilbert cell and thus causes much smaller distortion.
In the following, a lower voltage type mixer circuit 1300 will be described with reference to FIG. 14. Mixer circuit 1300 includes constant current sources 1035, 1036 which supply a constant current IEE, transistors 1031 to 1034, an inductor 1037, and a capacitor 1038. Here, in1, in2, Out+, and Outxe2x88x92 denote a first input signal, a second input signal, a positive first output current, and a negative first output current, respectively. The inductance of inductor 1037 is LE, and the capacitance of capacitor 1038 is CE.
Transistors 1031, 1032 have their emitter terminals connected commonly to each other, and transistors 1033, 1034 also have their emitter terminals connected commonly to each other. Transistors 1031, 1033 have their collector terminals connected commonly to each other, and transistors 1032, 1034 also have their collector terminals connected commonly to each other.
The common emitter terminal of transistors 1031, 1032 is connected to constant current source 1035 via node A. The common emitter terminal of transistors 1033, 1034 is connected to constant current source 1036 via node B. Inductor 1037 is provided between nodes A and B. Node B is connected to a ground via capacitor 1038. First input signal in1 is input to node A. Signal in2+ is input to the bases of transistors 1031, 1034, and signal in2xe2x88x92 is input to the bases of transistors 1032, 1033.
If inductor 1037 and capacitor 1038 satisfy f1 greater than 1/{2xcfx80√(LExc2x7CE)}, a signal which has its phase inverted by 180xc2x0 from that of input signal in1 can be obtained at node B.
However, the resistance component (emitter resistance in this case) of transistors 1033, 1034 at node B is small. As represented in the following expression, therefore, it is less possible that the phase difference between a voltage signal VA at node A and a voltage signal VB at node B attains 180xc2x0 as Recp becomes smaller.
It is noted that Recp is produced by parallel combination of the emitter resistance of transistors 1033, 1034 and it is small-signal equivalent resistance.
VB/VA=Recp/(1+jxcfx89xc2x7CExc2x7Recp)/{jxcfx89xc2x7LExc2x7Recp/(1+jxcfx89xc2x7CExc2x7Recp)}=Recp/{jxcfx89xc2x7LE+(Recpxe2x88x92xcfx89xc2x7xcfx89xc2x7LExc2x7CExc2x7Recp)}xe2x80x83xe2x80x83(21)
If the phase difference of the two signals does not attain 180xc2x0, the differential signal of the two signals is represented by the following expression. The amplitude of the two signals is 1, VA=sinxcfx89t, and VB=sin(xcfx89t+xcex8).                                                                                           V                  ⁢                                      xe2x80x83                                    ⁢                  A                                -                VB                            =                                                sin                  ⁢                                      xe2x80x83                                    ⁢                  ω                  ⁢                                      xe2x80x83                                    ⁢                  t                                -                                  sin                  ⁡                                      (                                                                  ω                        ⁢                                                  xe2x80x83                                                ⁢                        t                                            +                      θ                                        )                                                                                                                          =                              2                ⁢                                                      sin                    ⁡                                          (                                                                        -                          θ                                                /                        2                                            )                                                        ·                                      cos                    ⁡                                          (                                                                        ω                          ⁢                                                      xe2x80x83                                                    ⁢                          t                                                +                                                  θ                          /                          2                                                                    )                                                                                                                              (        22        )            
In other words, the input signal becomes smaller as the absolute value of xcex8 is smaller than 180xc2x0 as represented by expression (22). Thus, the conversion gain is reduced.
Since Recp used in expression (21) is nonlinear resistance which varies with second input signal in2, distortion is caused.
In the conventional mixer circuits as described above, the input signal becomes smaller as the absolute value xcex8 in expression (22) is smaller than 180xc2x0, and thus the conversion gain is reduced. Further, Recp as the parallel combination of the emitter resistance of transistors 1033, 1034 is nonlinear resistance which varies with second input signal in2, which causes distortion.
Therefore, the present invention provides a mixer circuit capable of realizing a high conversion gain.
A mixer circuit according to one aspect of the present invention includes: a first node to which a first input signal is input; a second input; a first output terminal from which a first component of an output signal is output; a second output terminal from which a second component of the output signal is output; a first transistor having a first control electrode to which a first component of a second input signal is input, a first electrode connected to the first output terminal, and a second electrode; a second transistor having a second control electrode to which a second component of the second input signal is input, a third electrode connected to the second output terminal, and a fourth electrode; a third transistor having a third control electrode to which the second component of the second input signal is input, a fifth electrode connected to the first output terminal, and a sixth electrode; a fourth transistor having a fourth control electrode to which the first component of the second input signal is input, a seventh electrode connected to the second output terminal, and an eighth electrode; a current source to supply a prescribed current to the first and second nodes; a phase conversion circuit provided between the first and second nodes to convert the phase of the first input signal and supply it to the second node; and a correction circuit provided between a first connection node for connecting the second and fourth electrodes and the first node or between a second connection node for connecting the sixth and eighth electrodes and the second node.
Preferably, the correction circuit includes a first impedance element, which is not open to direct current, provided between the first connection node and the first node, and a second impedance element, which is not open to direct current, provided between the second connection node and the second node. Alternatively, the correction circuit includes a first resistance element provided between the first connection node and the first node, and a second resistance element provided between the second connection node and the second node.
Therefore, the phase difference between signals at the first and second nodes becomes 180xc2x0 and the conversion gain is increased.
Preferably, the correction circuit includes a first inductor provided between the first connection node and the first node, and a second inductor provided between the second connection node and the second node. Alternatively, the correction circuit includes a transformer having a first inductor provided between the first connection node and the first node and a second inductor provided between the second connection node and the second node.
Therefore, the harmonic components of signals at the first and second nodes, which are input to the common emitter terminal of the first and second transistors and the common emitter terminal of the third and fourth transistors, can be reduced. Since the direct current loss in the inductors is small, the mixer circuit is especially suitable for low voltage operation.
Preferably, the correction circuit includes a first filter provided between the first connection node and the first node, and a second filter provided between the second connection node and the second node.
Therefore, the harmonic components of signals at the first and second nodes, which are input to the common emitter terminal of the first and second transistors and the common emitter terminal of the third and fourth transistors, can be reduced.
Preferably, the phase conversion circuit includes an inductor connected between the first and second nodes, and a capacitance element connected between the second node and a node supplied with a ground voltage. Alternatively, the phase conversion circuit includes a 180xc2x0 phase converter to convert the phase of a signal at the first node by 180xc2x0 and supply it to the second node.
Preferably, the mixer circuit further includes a fifth transistor connected between the first connection node and the correction circuit and receiving a prescribed bias voltage at a control electrode, and a sixth transistor connected between the second connection node and the correction circuit and receiving a prescribed bias voltage at a control electrode.
Therefore, the distortion in the mixer circuit can be reduced.
The present invention also provides a mixer circuit capable of realizing a high conversion gain and reducing distortion.
A mixer circuit according to a further aspect of the present invention includes: a first node to which a first input signal is input; a second node; a first output terminal from which a first component of an output signal is output; a second output terminal from which a second component of the output signal is output; a first transistor having a first control electrode to which a first component of a second input signal is input, a first electrode connected to the first output terminal, and a second electrode; a second transistor having a second control electrode to which a second component of the second signal is input, a third electrode connected to the second output terminal, and a fourth electrode; a third transistor having a third control electrode to which the second component of the second input signal is input, a fifth electrode connected to the first output terminal, and a sixth electrode; a fourth transistor having a fourth control electrode to which the first component of the second input signal is input, a seventh electrode connected to the second output terminal, and an eighth electrode; a current source to supply a prescribed current to the first and second nodes; a phase conversion circuit provided between the first and second nodes to convert the phase of a signal at the first node and supply it to the second node; a fifth transistor provided between a first connection node for connecting the second and fourth electrodes and the first node and having a fifth control electrode receiving a prescribed bias voltage; and a sixth transistor provided between a second connection node for connecting the sixth and eighth electrodes and the second node and having a sixth control electrode receiving a prescribed bias voltage.
Therefore, the distortion in the mixer circuit can be reduced.
Preferably, the phase conversion circuit includes an inductor connected between the first and second nodes, and a capacitance element connected between the second node and a node supplied with a ground voltage. Alternatively, the phase conversion circuit includes a 180xc2x0 phase converter to convert the phase of a signal at the first node by 180xc2x0 and supply it to the second node.
Preferably, the mixer circuit further includes a first inductor provided between the first node and the fifth transistor, and a second inductor provided between the second node and the sixth transistor.
Therefore, the harmonic components of signals at the first and second nodes, which are input to the common emitter terminal of the first and second transistors and the common emitter terminal of the third and fourth transistors can be reduced. Since the direct current loss in the inductors is small, the mixer circuit is especially suitable for low voltage operation.
Preferably, the mixer circuit further includes a first impedance element, which is not open to direct current, provided between the first node and the fifth transistor, and a second impedance element, which is not open to direct current, provided between the second node and the sixth transistor.
Therefore, the phase difference between signals at the first and second nodes becomes 180xc2x0 and the conversion gain is increased.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.